1. Field of the Invention
The present invention relates to a memory device and method of performing write operations in such a memory device.
2. Description of the Prior Art
It is generally desirable to seek to reduce the power consumption of a data processing apparatus, and such a data processing apparatus often includes a memory device for storing the data used by the data processing apparatus. Power consumption is particularly an issue in hand held or mobile devices such as laptops, mobile phones, PDAs, etc, since the power consumption of such a device has a large impact on the battery life. One approach for seeking to reduce power consumption of a device is to lower the supply voltage used, since lowering the supply voltage reduces the power consumption by a square law. Hence, there are significant benefits in reducing the supply voltage to a device such as a system-on-chip (SoC). Often, SoC devices have large embedded memory devices such as SRAM devices, and the total capacity of the embedded SRAM devices is increasing. Therefore, the proportion of power consumption associated with the memory device is significant and will continue to increase as memory capacity increases.
Whilst lowering supply voltage can significantly reduce power consumption, it can cause problems, particularly in respect of the operation of memory devices. A significant barrier to achieving low voltage memory devices is the increase in process variation that occurs with process scaling. In particular, as the individual memory cells are made smaller and smaller, the device characteristics of the cells vary significantly due to dopant fluctuation and other effects. This causes stability problems within the individual memory cells, and this stability problem is aggravated at lower operating voltages. In particular, a reduction in the nominal supply voltage is accompanied by a reduction in device noise margins, making components more vulnerable to power supply noise. This noise consists of AC noise caused by the dynamic AC voltage fluctuation due to the frequency-dependent distributed parasitics inherent in power distribution systems, and DC noise caused by capacitive mismatch. Further, a DC voltage drop causes a reduction in the signal, and as a result of this DC voltage drop the signal to noise margin (SNM) reduces (because the value of the signal is reduced). The DC voltage drop is often referred to as the IR drop, according to Ohm's law V=I×R, where R is the equivalent path DC resistance between the source location and the device location, and I is the average current the chip draws from the supply. Hence, the more embedded a particular memory device is within the SoC, the higher the IR drop will be, and hence the greater the noise, thereby further reducing the stability of the cells. In particular, such noise can cause the state stored in individual memory cells to flip and it is accordingly important to try and avoid this occurring. To provide resistance to noise, it is generally required to make some of the individual transistors making up each memory cell relatively large, since this can improve the cell's resilience to noise. However, when such transistors are made larger, it has a negative impact on the writeability of the cell, in that the write operation will typically take longer when larger cells are used.
In summary, it is desirable to reduce supply voltages to a memory device so as to reduce power consumption. However, as memory devices become smaller, there is an increase in process variation which causes a stability problem that is aggravated when using low supply voltages. In seeking to provide resilience to this stability problem, a side effect is that writeability tends to become compromised.
The Article “90-nm Process-Variation Adaptive Embedded SRAM Modules with Power-Line-Floating Write Technique”, by M Yamaoka et al, IEEE Journal of Solid State Circuits, Volume 41, No. 3, March 2006, discusses the writeability problem, and describes a power-line-floating technique which improves the speed of the write operation under lower supply voltage. In accordance with the technique described therein, the power supply to an addressed memory cell is made to float when that memory cell is accessed for writing. Before the data flip that occurs during the write operation, write current flows through a load transistor and transfer transistor of the memory cell, as shown in FIG. 4(a) of that article, and this write current decreases the supply voltage and enables the write margin to be improved. Whilst controlling the supply voltage in such a way improves the write margin, and hence increases write speed, it tends to decrease the data retention stability of the cell.
Further, a PMOS isolation transistor is provided to form the switch used to enable the supply voltage to enter a floating state during the write operation. In particular, the PMOS isolation transistor is turned off at the start of the write operation to cause the supply voltage to float. However, when a write operation is not being performed, the PMOS isolation transistor is turned on, and the PMOS on-resistance gives rise an IR drop associated with that component which thereby gives a lower effective supply voltage at the memory cell, thereby reducing the static noise margin and hence reducing the stability of the cell. Further, the slightly reduced effective supply voltage is likely to slow down the read operation.
As an additional issue, there is a limit on the number of cells that can share the same PMOS isolation transistor, as decided by the capacitance of the floating line. In particular, the more cells that the isolation transistor is shared with, the higher the capacitance on the floating line, and the less the performance improvement of the write operation. At some point, the capacitance will reach a point where no improvement in the speed of a write operation occurs. As a result, a significant number of such PMOS isolation transistors will be required, and this will have a significant impact on area, and hence the cost, of a device constructed in such a manner.
Accordingly, it would be desirable to develop an improved technique for improving writeability in memory devices arranged to operate at low supply voltages.